eLABa objektas:   "Testų sudarymo metodų vėlinimo gedimams tyrimas", 2008,D:20080710:145321-50124
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ETD (LT)
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URL nuoroda http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2008~D_20080710_145321-50124
Dokumentas Magistro darbas
Prieigos teisės Laisvai prieinamas internete.
Institucija Kauno technologijos universitetas
Mokslo kryptis 07 T - Informatikos inžinerija
Atsakomybė Radavičius, Marius - Magistro baigiamojo darbo autorius
Jokužis, Vytautas - Magistro baigiamojo darbo vertinimo komisijos pirmininkas
Jusas, Vacius - Magistro baigiamojo darbo vertinimo posėdžio sekretorius
Bareiša, Eduardas - Magistro baigiamojo darbo vertinimo komisijos narys
Kazanavičius, Egidijus - Magistro baigiamojo darbo vertinimo komisijos narys
Šeinauskas, Rimantas - Magistro baigiamojo darbo vertinimo komisijos narys
Jusas, Vacius - Magistro baigiamojo darbo vadovas
Misevičius, Alfonsas - Magistro baigiamojo darbo recenzentas
Kauno technologijos universitetas - Mokslinį laipsnį teikianti institucija
Antraštė (-ės) Testų sudarymo metodų vėlinimo gedimams tyrimas
Research and Development of Test Generation Methods for Delay Faults
Santrauka [EN]

The object of this work is to research functional test generation methods for delay faults. Manufacturing of programmable chips always has possibility that in those systems will be delay faults that means: input signal for some reasons appear in the output after longer time than the time was definite.

In our days, programmable chips are used in the industry for the management of various civil and military manufacturing processes, for instance medicine. Delay fault testing is very important part for the system safety and trustiness. Today those requests become higher and higher, because human safety is common importance.

Created test generation algorithm of the functional test that is based solely on the primary input values and the primary output values of the programming prototype. System was tested by simple step by step model,(which is presented in the fourth part of this document). The obtained results are useful and acceptable. All results are presented in the appendix of this document. The experiment contains 24 logic schemas processed test generation algorithm.

The work includes of 42 pictures, 27 tables and conceptual dictionary. 15 bibliographical sources have been used.

Raktažodžiai: delay faults, test generation, algoritms